1. Field of the Invention
The present invention generally relates to data driven information processors, and more particularly, to a technique of forming a data packet in a data driven information processor.
2. Description of the Related Art
In a conventional von Neumann computer, a plurality of instructions constituting a program are prestored in a program memory. By a program counter specifying addresses of a program memory sequentially, instructions are read out from the program memory to be executed.
On the other hand, a data driven information processor is one kind of non Neumann computers not having a concept of a successive execution of instructions by a program counter. The data driven information processor employs an architecture based on parallel processing of instructions. In the data driven information processor, as soon as data to be subjected to operation is available, instructions can be executed. Since a plurality of operations, driven by data, are carried out simultaneously, programs are carried out in parallel according to a natural flow of data. Therefore, significant reduction of a time required for operation can be expected.
The data driven information processor generally forms a data packet as shown in FIG. 1, for example. The data packet includes a data portion in which data to be subjected to processing is stored, and a tag portion in which destination information of the data is stored. The tag portion includes a generation number and a destination number. The generation number is an identifier assigned to each data group for distinguishing the data groups from each other when the data driven information processor processes a plurality sets of data groups. The destination number is an identifier assigned to each data packet for distinguishing data packets belonging to a certain generation from each other. The number of kinds of the destination number is usually the same as the number of input data of a certain generation in a program to be executed. The data driven information processor applies desired processing to each data by sending the data packet to a pipeline.
In forming a data packet, it is necessary to apply input data as well as destination information corresponding to the data. Much labor is required when such destination information is generated by manual operation.
Japanese Patent Laying-Open No. 64-26236 (data driven computer), for example, makes a suggestion for reducing workload of forming a data packet. According to the technique disclosed in this literature, as far as data are input to the data driven computer in a predetermined order, destination information is automatically added to the input data. Even if information of a destination address or the like is not applied, processing results are provided in a predetermined order. Also, in this literature, input data packets are divided into generations for every predetermined number of packets in order to distinguish a plurality sets of data groups from each other. The same generation number is applied to data packets belonging to a certain generation. As a result, data processing can be carried out without inconsistency.
Consider the case where an object to be processed by the data driven information processor is image information as shown in FIG. 2, for example. Data to be processed can be considered three-dimensional data specified by three elements, that is, field, line, and pixel. It is necessary to distinguish these three dimensions in processing the image information. On the other hand, a generation number is for distinguishing data belonging to different data groups, as described above. Operation processing between data packets of different generation numbers leads to inconsistent results. Therefore, image information must be processed on the basis of generations and dimensions.
However, generation numbers were formed in a conventional data driven information processor by simply dividing input data packets into generations in an order of input, and simply assigning an increasing natural number to generations as shown in FIG. 3. Therefore, the conventional data driven information processor sometimes required input of data in a special order to process multidimensional data. Furthermore, the conventional data driven information processor was not sometimes able to process data efficiently.
In order to detect a control signal for automatically generating destination information in the conventional data driven information processor, a detecting circuit as shown in FIG. 4, for example, was used. Let RIN.sub.n be an input signal of a cycle n, and ROUT.sub.n be an output signal, the circuit is configured so that the following logical expression holds: EQU ROUT.sub.n+1 =RIN.sub.n . . . (1)
It should be noted that the input signal RIN corresponds to a control signal, and the output signal ROUT corresponds to a detected control signal. This circuit operates so that the value of the input signal RIN.sub.n when a clock signal CK rises attains the value of the output signal ROUT.sub.n+1.
Consider the case shown in FIG. 5, for example. Referring to FIG. 5, the clock signal CK rises from an "L" level to an "H" level at times t1,t2, t3, t4, t5, t6 and t7, and falls from the "H" level to the "L" level at respective intermediate times. Assume that the input signal RIN is initially at the "H" level, switches to the "L" level at time t1', and again rises to the "H" level at time t2'. Assume that the input signal RIN again falls to the "L" level at time t4'.
Since the input signal RIN falls from the "H" level to the "L" level at time t1', an output signal Q of a D type flip-flop shown in FIG. 4 falls from the "H" level to the "L" level at time t2 in response to a rising of the clock signal CK. Since the input signal RIN rises from the "L" level to the "H" level at time t2', the output signal Q rises from the "L" level to the "H" level at time t3 in response to a rising of the clock signal CK.
The output signal Q is directly output as the output signal ROUT. The output signal ROUT attains the "L" level during a time period t2-t3, and attains the "H" level during a time period t3-t5. More specifically, the "L" level of the output signal ROUT during the time period t2-t3 is detected as a control signal.
Since the output signal ROUT attains the value of the input signal RIN at a rising of the clock signal CK, however, a control signal detecting circuit shown in FIG. 4 has the following problems. Assume that a detected period of the control signal must be equal to one cycle of the clock signal CK. Also assume that, when the detected control signal is at the "L" level for one cycle, the detected control signal must always return to the "H" level in the next cycle.
In order to maintain the detected control signal at the "L" level over one cycle of the clock signal CK during the time period t2-t3 and to bring the detected control signal to the "H" level in the next cycle, the input signal RIN must be always switched to the "H" level during the time period t2-t3 (for example, at t2') after the "L" level during the time period t1-t2 (for example, at t1'). Otherwise, the output signal ROUT remains at the "L" level. When the input signal RIN is brought to the "L" level at time t4' of FIG. 5, and maintained low, for example, the output signal ROUT stays at the "L" level.
As described above, the input signal RIN must be always returned to the "H" level after once attaining the "L" level, resulting in intricate generation mechanism of the input signal RIN. When the cycle of the clock signal CK is short, it is sometimes difficult to switch the input signal RIN between the "L" level and the "H" level in such a short cycle.